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Validation in a component-based design flow for multicore SoCs

Auteur(s) : G. Nicolescu, S. Yoo, A. Bouchhima, A. A. Jerraya

Doc. Source: 15th International Symposium on System Synthesis (ISSS'02)

Publisher : ACM, NY, USA

Pages : 162-167

Doi : 10.1145/581199.581236

Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable this integration, we use a design approach called component based-design approach. In this approach, the validation of system integration takes most of design efforts. This paper presents an automatic method of SoCs design validation. Based on a generic simulation wrapper architecture, the presented method provides automatic generation of executable models throughout different stages of SoC design flow. A case study of validating a VDSL application shows the effectiveness of the method.