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Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

Auteur(s) : Saif-Ur Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin-Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi

Doc. Source: IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14)

Publisher : IEEE

Pages : 553-558

Doi : 10.1109/ISVLSI.2014.66

Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness.