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Cost-efficient of a cluster in a mesh SRAM-based FPGA

Auteur(s) : Saif-Ur Rehman, M. Benabdenbi, L. Anghel

Doc. Source: IEEE 20th International On-Line Testing Symposium (IOLTS'14)

Publisher : IEEE

Pages : 75-80

Doi : 10.1109/IOLTS.2014.6873675

This paper presents a cost-efficient Built-In Self-Test (BIST) scheme for fault detection and diagnosis of a cluster in a mesh FPGA. In this scheme, test cost reduction is achieved by simultaneous testing of logic and intra-cluster interconnect resources without degradation of diagnostic resolution. We analyze the impact of cluster size variation on the testability of a given cluster. Efficiency of this scheme is calculated in terms of the number of test configurations and the corresponding fault coverage for different cluster sizes. Moreover, automated tools developed for BIST implementation are integrated into the standard design flow for bitstream generation. Experimental results show that 100% stuck-at fault coverage can be obtained for a cluster with a gate level diagnostic resolution.