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Application-independent testing of multilevel interconnect in mesh-based FPGAs

Auteur(s) : Saif-Ur Rehman, M. Benabdenbi, L. Anghel

Doc. Source: IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15)

Publisher : IEEE

Pages : 1-6

Doi : 10.1109/DTIS.2015.7127383

This paper presents a BIST scheme for a new hierarchical interconnect topology in mesh FPGAs. The proposed technique ensures full test and diagnosis by performing selection of test paths. It uses 2×2 adjacent logic resources. Using this scheme, any N×N FPGA array can be further tested by N parallel 2×2 array procedure which ultimately reduces the test time. The efficiency of this scheme is evaluated in terms of the number of configurations required for a complete testing of global interconnect in cluster-based FPGAs for different cluster sizes. Automated tools are developed to generate the test configuration bitstreams and to integrate them into a standard FPGA CAD flow. Simulation results show that 100% test coverage for stuck-at and pair-wise bridging faults can be achieved with high diagnostic resolution.