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Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology

Auteur(s) : O. Rolloff, R. Possamai Bastos, L. Fesquet

Doc. Source: 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'15)

Publisher : IEEE

Reducing voltage is a traditional strategy for designing and activating low-power mode of integrated systems. Low voltages otherwise make slower components that can cause critical timing violations in synchronous circuits. On the contrary, asynchronous circuits, which have no clock constraints, are capable to adapt to delay variations. This paper presents the minimum operation voltages of the fundamental asynchronous components, the C-elements, on recent FD-SOI 28-nm technology. Results show that conventional scheme of the C-element can reduce power by a factor of 34 for the less consuming scheme if operating at minimum voltage of 0.28 V instead of nominal 1.00 V. In addition, a low-voltage conventional C-element on FD-SOI 28-nm with RVT transistor consumes about one-third of the power of its counterpart on bulk 65-nm CMOS technology.