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Guidelines on 3D VLSI design regarding the intermediate BEOL process influence

Auteur(s) : A. Ayres, O. Rozeau, B. Borot, L. Fesquet, G. Cibrario, P. Batude, M. Vinet

Doc. Source: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Publisher : IEEE

Pages : 1-2

Doi : 10.1109/S3S.2015.7333540

This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.