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Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options

Auteur(s) : K. Chibani, S. Bergaoui, M. Portolan, R. Leveugle

Doc. Source: IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Publisher : IEEE

Pages : 778-781

Embedded software is at the heart of many systems, including critical ones. It is therefore often mandatory to precisely identify, for a given application, the robustness level achieved with respect to various perturbations. This paper is focused on soft errors occurring in internal registers of pipelined processors. Two criticality evaluation approaches are compared; one based on criteria evaluated statically at compile time and one based on an analytical model of the processor architecture. The differences between the two evaluations are analyzed, both in terms of precision and in terms of evaluation time. Also, the impact of the compilation optimizations on the achieved robustness is revisited on the basis of the processor model.