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Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor

Auteur(s) : K. Chibani, M. Ben Jrad, M. Portolan, R. Leveugle

Doc. Source: 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14)

Publisher : IEEE

Pages : 260-265

Doi : 10.1109/VLSI-SoC.2014.7004158

The probability of application failures due to soft errors in microprocessors is directly related to the lifetime of data stored in the internal registers. For high performance processors, the accurate analysis of this lifetime is difficult due to the various micro-architecture features, including pipeline registers and fast-forwarding connections managing data dependencies. Using fault injections to evaluate the robustness of a given application program is very time-consuming, even when emulation is used. In consequence, the comparison of several program implementations is often not affordable. We propose a new approach for the evaluation of lifetimes in all the registers of a pipelined processor, ensuring accurate results while reducing drastically the time required for evaluation, thus enabling more software optimizations. In addition, the most critical registers can be quickly identified.