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Efficient link-level error resilience in 3D NoCs

Auteur(s) : V. Pasca, Saif-Ur Rehman, L. Anghel, M. Benabdenbi

Doc. Source: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12)

Publisher : IEEE

Pages : 127 - 132

Doi : 10.1109/DDECS.2012.6219038

Due to their scalability and flexibility, Networks-on-Chip are among the most popular communication fabrics for 3D integrated systems. 3D NoCs consist of a mix of inter-die and intra-die links implemented in different technologies. Thus, in order to guarantee correct data transmission through the 3D NoC, link reliability must be ensured. Error resilience techniques have been developed to protect links at the expense of increased area and power consumption, and reduced performance. In this paper, error resilience schemes are implemented for NoC links in stacked 3D integrated systems. We analyze, with respect to area / power overheads and reliability, the impact of inter-die and intra-die link-level error resilience techniques on a 3D NoC router architecture. Our results show that inter-die link protection with correction-based schemes and interleaved single error correction (SEC) codes are more efficient than traditional protection on all links.