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On error models for RTL security evaluations

Auteur(s) : P. Vanhauwaert, P. Maistri, R. Leveugle, A. Papadimitriou, D. Hély, V. Beroulle

Doc. Source: 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14)

Publisher : IEEE

Pages : 115-120

Doi : 10.1109/DTIS.2014.6850666

Evaluating early at design time the level of security achieved with respect to fault-based hardware attacks requires understanding and accurately modeling the faults that can actually occur in a circuit under attack. Attacks with lasers can produce single or multiple-bit errors, while having a local impact in the circuit. This paper discusses several fault or error models that can be considered at design time and summarizes experimental results providing some insights into the consequences of the model chosen for evaluation.