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Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization

Auteur(s) : M.M. Hamayun, F. Pétrot, N. Fournel

Doc. Source: Asian South-Pacific Design Automation Conference (ASP-DAC'13)

Publisher : IEEE

Pages : 576-581

Doi : 10.1109/ASPDAC.2013.6509660

We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.