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BIST of interconnection lines in the pixel matrix of CMOS imagers

Auteur(s) : R. Fei, J. Moreau, S. Mir

Doc. Source: 5th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI'13)

Publisher : IEEE

Pages : 174-177

Doi : 10.1109/IWASI.2013.6576068

Interconnection lines in the sensors of CMOS imagers are used for pixel bias, addressing and readout. Catastrophic faults in these lines can cause parts of the pixel matrix to operate incorrectly and produce image defects like residual stripes and bands in images. These kinds of image defects are often difficult to remove by the image processing correction algorithm, and they are clearly visible as a sort of noise pattern. Among the defects in the pixel array, these catastrophic faults have most important influence on yield. In addition, partially degraded metal lines cannot be detected on todays' standard industrial testers for image sensors. These defects can evolve into catastrophic faults and they are the main cause of customer returns for many products. This paper proposes two built-in self-test (BIST) solutions to catch these defects in the pixel array, taking into account the industrial test constraints, namely increase of fault coverage, decrease of test time and test cost minimization.