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BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA

Auteur(s) : Saif-Ur Rehman, M. Benabdenbi, L. Anghel

Doc. Source: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13)

Publisher : IEEE

Pages : 296 - 301

Doi : 10.1109/DFT.2013.6653622

This paper presents new Built-In Self-Test (BIST) schemes for fault detection and diagnosis of Basic Logic Element (BLE) and intra-cluster (local) interconnect of a novel mesh of cluster FPGA. The proposed schemes avoid redundant test/diagnosis configurations by merging multiple configurations without losing diagnostic resolution. Efficiency of these schemes is calculated in terms of respective number of test/diagnosis configurations for the new FPGA. Results show that 50 BIST configurations are required for a complete test and diagnosis of the cluster. The testability aspects of this FPGA are explored in comparison with the classic clustered-mesh FPGA of the same parameters.