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SyntHorus-2: Automatic Prototyping from PSL

Auteur(s) : K. Morin-Allory, N. Javaheri, D. Borrione

Doc. Source: IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13)

Publisher : IEEE

Pages : 75-80

We propose a linear complexity approach to achieve the automatic synthesis of designs from declarative temporal specifications. From each property, we produce a component that combines the features of signal monitors and generators: the reactant. This paper gives a formalization of a method to automatically decide which signals are observed and which are generated. The method is efficient, and synthesizes control circuits in a few seconds.