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Accurate estimation of analog test metrics with extreme circuits

Auteur(s) : K. Beznia, A. Bounceur, L. Abdallah, K. Huang, S. Mir, R. Euler

Doc. Source: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12)

Publisher : IEEE

Pages : 272 - 275

Doi : 10.1109/ICECS.2012.6463748

Specification-based testing of analog/RF circuits is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-In Test (BIT) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage, before the real production, by estimating parametric test errors such as Test Escapes (TE) and Yield Loss (YL). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. Since these extreme circuits are rare events, they cannot be obtained with a Monte Carlo simulation of an affordable size. However, statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. In this paper, we will demonstrate this technique for the evaluation of an RF LNA BIT technique for which a large database of 106 circuits has been simulated for comparison purposes.