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Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces

Auteur(s) : S. Foroutan, H. Sheibanyrad, F. Pétrot

Doc. Source: The Design Automation Conference (DAC'12)

Publisher : ACM, NY, USA

Pages : 366-375

Doi : 10.1145/2228360.2228427

This paper addresses link-buffer capacity allocation in the design process of best-effort 3DNoCs holding hotspot memory ports. We show that in 3DSoCs with integrated wide I/O DRAMs, the congestion spreading is different from SoCs with external DRAMs: the bottlenecks are not anymore the external memory ports but the network links that become saturated and retropropagate the congestion. The distribution of bottleneck links is directly affected by the traffic directed to the hot memory ports. Using an analytical performance evaluation method, we determine network link buffer capacities according to the given workload composed of regular and hotspot traffics.