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Physical design of HW interfaces for MPSoC

Auteur(s) : I. Petkov, P. Amblard, M. Hristov, A. A. Jerraya

Doc. Source: 7th International Symposium on Microelectronics Technologies and Microsystems in cooperation with 12th International Scientific and Applied Science Conference ELECTRONICS 2003

Publisher : Technical Univ. of Sofia, Sofia, Bulgaria

Pages : 230-235

This paper presents the stage of physical design flow of automatic generated hardware communication wrappers for ARM processors. This paper focuses on the study of automatically generated RTL models and the definition of an effective model for physical integration. The type of design treated in this work applies primarily to the design of the application specific integrated circuits ASIC designed at the base of the standards cells.