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Pattern-based injections in processors implemented on SRAM-based FPGAs

Auteur(s) : M. Ben Jrad, R. Leveugle

Doc. Source: 13th Latin-American Test Workshop (LATW'12)

Publisher : IEEE

Pages : 200-203

Doi : 10.1109/LATW.2012.6261263

Multiple errors are an increasing concern for designers. Multiple errors in the configuration memory have to be taken into account when a circuit is implemented on a SRAM-based FPGA. This paper reports on the impact of realistic multiple-bit errors in the configuration, with respect to the robustness of a processor with error detection mechanisms.