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Design for Test and Reliability in Ultimate CMOS

Auteur(s) : M. Nicolaidis, L. Anghel, N.-E. Zergainoh, Y. Zorian, T. Karnik, K. Bowman, J. Tschanz, S.-L. Lu, C. Tokunaga, A. Raychowdhury, M. Khellah, J. Kulkarini, De Vivek, D. Avresky

Doc. Source: Design, Automation and Test in Europe (DATE'12)

Publisher : EDAA Publishing Association - CMP, Grenoble, France

Pages : 677-682

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.