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Spidergon STNoC design flow

Auteur(s) : F. Dubois, J. Cano, M. Coppola, J. Flich, F. Pétrot

Doc. Source: IEEE/ACM International Symposium on Networks on Chip (NoCS’11)

Publisher : IEEE

Pages : 267 - 268

In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.