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Memory BIST with address programmability

Auteur(s) : A. Fradi, M. Nicolaidis, L. Anghel

Doc. Source: IEEE international On Line Testing Symposium (IOLTS'11)

Publisher : IEEE

Pages : 79 - 85

Doi : 10.1109/IOLTS.2011.5993815

In modern SoCs embedded memories concentrate the majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test, leading to field failures due to the use of faulty components in final products. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage for a increasingly complex faults. Fixing the test algorithm during the design phase may not be compatible with this goal, as unexpected failures not covered by this algorithm may be occur during production. Also, having the possibility to select the memory test algorithm after fabrication is very important during the initial phase of a new process node (both process debug and production ramp-up). Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. BIST approaches enabling test algorithm programmability and data background programmability at low area cost have been presented in the past. However, no proposals exist for programming the address sequence used by the test algorithm. In this paper we expend programmable BIST to include address programmability. This new feature is implemented at low cost by using the memory under test itself to store the desired address sequence and some compact circuitry that enables using this sequence for testing the memory.