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Interconnect Built-In Self-Repair and Adaptive Serialization (I-BIRAS) in 3D Integrated Systems

Auteur(s) : M. Nicolaidis, V. Pasca, L. Anghel

Doc. Source: 16th IEEE European Test Symposium (ETS'11)

Publisher : IEEE

Pages : 208 - 208

Doi : 10.1109/ETS.2011.37

In 3D integrated systems, Thru-Silicon-Vias (TSVs) enable higher performance and energy efficiency, by reducing the data travel distances. However, the TSV manufacturing and wear-out defect rates lead to poor interconnect reliability and yield. The high fault rates and TSV footprint make spare-based repair solutions inefficient. I-BIRAS combines self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization. The design parameters are the number of data bits n, the number of spare TSVs r, and the minimum acceptable number mLIMIT of fault-free TSVs. If the number of fault-free TSVs is less than mLIMIT then the link assumed failed.