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Bottom-up digital system-level reliability modeling

Auteur(s) : N. Ruiz Amador, V. Huard, E. Pion, F. Cacho, D. Croain, V. Robert, S. Engels, P. Flatresse, L. Anghel

Doc. Source: Custom Integrated Circuits Conference (CICC'11)

Publisher : IEEE

Pages : 1 - 4

Doi : 10.1109/CICC.2011.6055343

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.