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10-gigabit throughput and low area for a hardware implementation of the Advanced Encryption Standard

Auteur(s) : P. Maistri, R. Leveugle

Doc. Source: 14th Euromicro/IEEE Conference on Digital System Design (DSD'11)

Publisher : IEEE

Pages : 266-269

Doi : 10.1109/DSD.2011.37

Current secure applications often need encrypted channels with high throughput, of the order of several gigabits per second. This level of performance is usually obtained with a considerable cost in terms of silicon area. In this paper, we present an implementation of the Advanced Encryption Standard based on heavy pipelining and partial unrolling, which is capable of a 10-Gbps throughput when encrypting with 128-bit keys.