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Resistance Increase Due to Electromigration Induced Depletion Under TSV

Auteur(s) : T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, A. Thuaire, R. El Farhane, F. Lorut, L. Anghel

Doc. Source: IEEE International Reliability Physics Symposium (IRPS’11)

Publisher : IEEE

Doi : 10.1109/IRPS.2011.5784499

3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the best of our knowledge, we propose for the first time an analytical model of resistance increase due to electromigration induced voiding in a line ended by a TSV.