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Reliability approach of high density Through Silicon Via (TSV)

Auteur(s) : T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, A. Thuaire, R. El Farhane, L. Anghel

Doc. Source: 12th Electronics Packaging Technology Conference (EPTC’10)

Publisher : IEEE

Pages : 321 - 324

Doi : 10.1109/EPTC.2010.5702655

This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV.