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An implementation of memory-based on-chip analogue test signal generation

Auteur(s) : S. Mir, L. Rolindez, C. Domingues, L. Rufer

Doc. Source: Asia and South Pacific Design Automation Conference (ASP-DAC'03)

Publisher : IEEE

Pages : 663-668

This paper presents a memory-based on-chip analogue test signal generation approach that is suitable for the test of an analogue and mixed-signal (AMS) core. This core contains programmable electronic interfaces for acoustic and ultrasound transducers. The test signals that must be generated on-chip have only low or moderate frequencies (10 Hz-10 MHz). The test circuitry designed in a 0.18 mu m CMOS technology includes a programmable shift-register, a clock divider, and a programmable switched-capacitor filter bank. By controlling the shift-register length and the sampling frequency, the paper shows that high quality single tone signals can be generated on chip in the band of interest.