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Ordering of analog specification tests based on parametric defect level estimation

Auteur(s) : N. Akkouche, S. Mir, E. Simeu

Doc. Source: 28th IEEE VLSI Test Symposium (VTS'10)

Publisher : IEEE

Pages : 301 - 306

Doi : 10.1109/VTS.2010.5469546

This paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order.