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Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks

Auteur(s) : V. Pasca, L. Anghel, C. Rusu, M. Benabdenbi

Doc. Source: European Test Symposium (ETS'10)

Pages : 258

3D integrated technology is a very attractive option for many advanced consumer products meeting specifications of the next generation of market key drivers such as mobile phones, set-top-boxes and HDTV. By replacing single chip packages with 3D devices, higher transistor density and low power saving are achieved. Moreover, data travel distances shortens and the manufacturing cost decreases through die reuse generalization. Networks-on-chip are among the design paradigms that benefit the most out of the 3D integration technology. Manufacturing processes of high density vertical wires are sub-optimal and the low yield and low densities of vertical interconnects make difficult the design of high performance communication fabrics. In this paper, a configurable fault tolerant vertical link is proposed for inter-die communication in stacked 3D systems. In 3D systems, face to high TSV defect densities, the link ensures correct inter-die communication and degrades its performance, as transmitted data is serialized and sent on functional vertical wires. For different 3D NoC configurations, the latency degradation under uniform traffic is up to 16% while the area overhead due to the link configuration fabric is up to 30%, as up to 75% of vertical wires are unavailable.