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Delay Insensitivity Does Not Mean Slope Insensitivity!

Auteur(s) : F. Ouchet, K. Morin-Allory, L. Fesquet

Doc. Source: IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10)

Publisher : IEEE

Pages : 176 - 184

Doi : 10.1109/ASYNC.2010.27

Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes in details this phenomenon and studies the robustness of different C-element topologies. The simulations, which have been performed in 130, 65 and 45 nm CMOS technologies, show an overview of the C-element behavior in presence of these slow ramps. This gives a comprehensive understanding of the phenomenon and suggests an appropriate approach for choosing the well-suited C-element topology for everybody facing these difficulties.