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Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies

Auteur(s) : L. Anghel, M. Nicolaidis

Doc. Source: International Conference on Artificial Neural Networks (IWANN'07)

Publisher : Springer

Pages : 422-429

Doi : 10.1007/978-3-540-73007-1

In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.