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Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL

Auteur(s) : Y. Oddos, K. Morin-Allory, D. Borrione

Doc. Source: International Conference On Very Large Scale Integration (VLSI-SoC'09)

Publisher : IFIP

We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. Each property is turned into a component combining monitor and generator features: the \\extgen. We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (i.e. CONMAX-IP and GenBuf) show the efficiency of the approach.