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Hierarchical parametric test metrics estimation: A sigma-delta converter BIST case-study

Auteur(s) : M. Dubois, H. Stratigopoulos, S. Mir

Doc. Source: 27th IEEE International Conference on Computer Design (ICCD’09)

Publisher : IEEE

Pages : 78-83

Doi : 10.1109/ICCD.2009.5413173

In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for Sigma Delta Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.