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Soft error circuit hardening techniques implementation using an automatic layout generator

Auteur(s) : C. Lazzari, L. Anghel, R. Reis

Doc. Source: IEEE Latin American Test Workshop (LATW'05)

Publisher : IEEE

Pages : 175-180

Soft error rates induced by cosmic radiation become unacceptable in future very deep sub-micron technologies. Many hardening techniques at different abstraction levels have been proposed to cope with increased soft error rates. Depending on the abstration level some techniques need to modify the design at transistor level, others required the modification of the circuit layout or to use new defined cells within the circuit. In this paper an Automatic layout generator is presented tio complete the system design process being able to easily generate the hardened design layout, thus reducing the system design time. This work aims at presenting the complete design of soft errors tolerant integrated circuit by using an automatic layout generator called Parrot Punch.