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Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies

Auteur(s) : L. Anghel, E. Kolonis, M. Nicolaidis

Doc. Source: IEEE Latin American Test Workshop (LATW'05)

Publisher : IEEE

Pages : 187-192

Transient and permanent fault densities are increasing in future submicron technologies. Thus more advanced solutions may be required to produce memories in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where future densities are predicted to be several order of magnitude higher than in current CMOS technologies. For such failure densities, nowadays memory architectures and repair techniques are not adequate. This work presents several memory cells architectures and methods addressing memories affected by high defect densities as well as evaluation of the area cost and performances.