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A flexible network-on-chip simulator for early design space exploration

Auteur(s) : C. Grecu, A. Ivanov, S. Saleh, C. Rusu, L. Anghel, P.P. Pande, V. Nuca

Doc. Source: 1st Microsystems and Nanoelectronics Research Conference (MNRC'08)

Publisher : IEEE

Pages : 33-36

Doi : 10.1109/MNRC.2008.4683371

The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.