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MYGEN: Automata-based On-line Test Generator for Assertion-based Verification

Auteur(s) : Y. Oddos, M. Boulé, K. Morin-Allory, D. Borrione, Z. Zilic

Doc. Source: 19th Great Lakes Symposium on VLSI (GLSVLSI'09)

Publisher : ACM, NY, USA

Pages : 75-80

Doi : 10.1145/1531542.1531563

To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monitors and generators, we have extended the monitor generator tool MYGEN to produce synthesizable on-line generators. We have tested the resulting generators in simulation and by emulation on an FPGA. The combination of multiple generators provides an efficient way to model the environment of modules within a DUT, facilitating an equivalent of software "unit testing" under real conditions, early in the design flow.