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An efficient architecture for the implementation of message passing programming model on massive multiprocessor

Auteur(s) : F. Gharsalli, A. Baghdadi, M. Bonaciu, G. Majauskas, W. Cesario, A. A. Jerraya

Doc. Source: 15th IEEE International Workshop on Rapid System Prototyping (RSP'04)

Publisher : IEEE

Pages : 80-87

Doi : 10.1109/IWRSP.2004.1311100

In this paper, we present a generic high performance architecture model for massive data transfer and computation applications. This application-specific architecture becomes crucial particularly for the design of emerging embedded video applications. Indeed, classic embedded system architectures have limited resources (clock frequency and memory) and consequently they cannot reach the required performance needed by emerging application. Moreover, the mapping of high level programming models (e.g. message passing) on fixed architectures introduces lots of software and communication overhead. This paper proposes an efficient architecture for the implementation of message passing programming model for MPSoC. Flexibility, scalability and high performance of this architecture are illustrated through the implementation of a real time embedded DivX video encoder.