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Soft Error Effect and Register Criticality Evaluations: Past, Present and Future

Auteur(s) : R. Leveugle, L. Pierre, P. Maistri, R. Clavel

Doc. Source: Workshop on Silicon Errors in Logic - System Effects (SELSE’09)

Publisher : IEEE

Pages : 15-20

Evaluating the robustness of digital circuits with respect to soft errors has become an important part of the design flow for many applications. The identification and hardening of the most critical registers is often necessary, while limiting the induced overheads. At the same time, the complexity of the circuits and the time to market pressure continue increasing. In this context, we briefly review the evolution of the techniques allowing a designer to evaluate the robustness early in the design flow and to identify the most critical elements. We discuss some limitations, then we propose new approaches to improve this process and we show some preliminary results.