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Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform

Auteur(s) : Y. Lechuga, A. Bounceur, R. Mozuelos, M. Martinez, S. Bracho, S. Mir

Doc. Source: 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08)

This paper presents a Design-for-Test method for folded and interpolated analog-to-digital converters. The test approach samples relative voltage deviations among internal circuit nodes. A fault simulation is used to establish the fault detection threshold of the BIST by using a CAT platform.