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Comparison of memory write policies for NoC based Multicore Cache Coherent Systems

Auteur(s) : P. Guironnet de Massas, F. Pétrot

Doc. Source: Proceedings of Design Automation and Test in Europe (DATE'08)

Publisher : IEEE

Pages : 997-1002

Doi : 10.1109/DATE.2008.4484811

The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work takes into account the difficulties related to on chip communication using network-like interconnects. Our study is based on Cycle Approximate Bit Accurate simulations (CABA) of platforms with up to 64 processors, modelling accurately all the aspects of multi-threaded program execution and memory accesses. Our main results show that write-through caches perform well compared to write-back ones, with a slightly simpler implementation and comparable traffic.