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Minimization of functional tests by statistical modelling of analogue circuits

Auteur(s) : N. Akkouche, A. Bounceur, S. Mir, E. Simeu

Doc. Source: International Conference on Design and Technology of Integrated Systems (DTIS’07)

Publisher : IEEE

Pages : 35-40

In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults.