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Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections

Auteur(s) : P. Maistri, P. Vanhauwaert, R. Leveugle

Doc. Source: International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07)

Publisher : IEEE

Pages : 499-507

Some protection techniques had been previously proposed for encryption blocks and applied to an AES encryption IP described at RT Level. One of these techniques had been validated by purely functional fault injections (i.e. algorithmic-level fault injections) against single- and multiple- bit errors. RT-Level fault injections have been performed recently on a few AES IPs and this paper summarizes the main results obtained, highlighting the new results and comparing the outcomes of the two fault injection levels.