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A novel double-data-rate AES architecture resistant against fault injection

Auteur(s) : P. Maistri, P. Vanhauwaert, R. Leveugle

Doc. Source: Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’07)

Publisher : IEEE

Pages : 54-61

Doi : 10.1109/FDTC.2007.4318985

Several techniques have been proposed for encryption blocks in order to provide protection against faults. These techniques usually exploit some form of redundancy, e.g. by means of error detection codes. However, protection schemes that offer an acceptable error detection rate are in general expensive, while temporal redundancy heavily affects the throughput. In this paper, we propose a new design solution that exploits temporal redundancy by DDR techniques without affecting adversely the throughput at lower clock frequencies. We will also show that the overall costs can be comparable to other solutions recently proposed.