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Réduction de tests fonctionnels par modélisation statistique des circuits analogiques

Auteur(s) : N. Akkouche, A. Bounceur, S. Mir

Doc. Source: 10ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’07)

The constant increase in the integration level of microelectronics technologies makes possible to manufacture more complex devices, including parts or blocks of heterogeneous nature. However, because of the difficulties of access to the blocks of a system, the problems of test become increasingly important, generating extremely high costs. This work addresses this problem by using a statistical modelling of the performances of the analogue blocks for the optimization of the functional test. The method suggested is based on the evaluation of test metrics, in particular the defect level like criterion of elimination of the performances to be tested. This makes possible during the production test to classify the functional and failing circuits with an optimal number of measurements of test and a reduction of the total test time.