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On-line test vector generation from temporal regular expressions

Auteur(s) : Y. Oddos, K. Morin-Allory, D. Borrione

Doc. Source: Intensive Workshop on Service Oriented Computing (IWSOC'06)

Publisher : IEEE

Pages : 135-140

We propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a "SERE" formula, we build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation.