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Semi-formal verification tool implementation using introspection mechanisms in a System-Level Design environment

Auteur(s) : M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E.M. Aboulhamid

Doc. Source: Forum on specification & Design Language (FDL’06)

Publisher : ECSI

Pages : 265-271

Verification tools are part of new generation of CAD tools, mandatory to cope with the growing complexity of System-On-Chip. We believe that all these tools should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET Framework. It takes advantage of advanced programming features which facilitates the integration of external tools, such as semi formal verification tools. This paper presents the implementation of a semi-formal verification tool for ESys.NET. We show that by using Introspection to retrieve the state of the model during simulation and to check a set of user defined rules, neither the model nor the simulator is modified by the added verification capabilities.