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On-line test vector generation from temporal constraints written in PSL

Auteur(s) : Y. Oddos, K. Morin-Allory, D. Borrione

Doc. Source: Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06)

Publisher : IFIP

Pages : 397-402

We propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a “foundation language” formula, we build a synthetizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthetized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation.