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Scheduler implementation in MPSoC Design

Auteur(s) : Y. Cho, S. Yoo, K. Choi, N.-E. Zergainoh, A. A. Jerraya

Doc. Source: Asia South Pacific Design Automation Conference (ASP-DAC'05)

Publisher : IEEE

Pages : 151-156

Doi : 10.1109/ASPDAC.2005.1466148

In the design of a heterogeneous multiprocessor system on chip, we face a new design problem, scheduler implementation. In this paper, we present an approach to implementing a static scheduler, which controls all the task executions and communication transactions of a system according to the order of pre-determined schedule. For the scheduler implementation, we consider intra/inter-processor synchronization. We also consider scheduler overhead, which is often neglected. In particular, we address the issue of centralized implementation versus distributed implementation. We investigate the pros and cons of the two different scheduler implementations. Through experiments with synthetic examples and a real world multimedia application, we show the effectiveness of our approach.