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Prof. Vojin G. Oklobdzija, ACSEL Laboratory

Theme: Energy Minimization Method for Optimal Energy-Delay
Date: le mardi 15 juin 2004 de 9h00 à 12h00, Salle T312, Entrée T de l'INPG, 46 avenue Félix Viallet , 38031 GRENOBLE

Biography

Vojin G. Oklobdzija, is an IEEE Fellow and Distinguished Lecturer of the IEEE Solid-State Circuits Society. He received a Dipl. Ing. degree from the Electrical Engineering Department of the University of Belgrade in 1971, and his Ph.D. from the University of California at Los Angeles in 1982. From 1982 to 1991 he was at the IBM Thomas J. Watson Research Center, where he made contributions to the development of RISC processors and supercomputer design. In the course of this work, he obtained several patents, the most notable one on register renaming, which enabled a new generation of computers. From 1988 to 1990 he was an IBM visiting faculty member at the University of California at Berkeley. Since 1991, he has been a professor at the University of California and has served as a consultant to many companies, including: Sun Microsystems, Bell Laboratories, Hitachi, Fujitsu, SONY, Intel, Samsung and Siemens Corp. where he was a principal architect for the Infineon TriCore processor. He holds 12 U.S., 7 international and 5 other patents pending. Prof. Oklobdzija serves as associate editor for the IEEE Transaction on Computers, IEEE Transactions on VLSI Systems, Journal of VLSI Signal Processing and IEEE MICRO. He served on the ISSCC program committee from 1996 to 2003 among numerous other conference committees. He was a General Chair of the 13th Symposium on Computer Arithmetic. Prof. Oklobdzija has published more than 140 papers, three books and dozen of book chapters in the areas of circuits and technology, computer arithmetic and computer architecture. He has given over 150 invited talks and short courses in the USA, Europe, Latin America, Australia, China and Japan. (for further information please see: http://www.ece.ucdavis.edu/acsel )

Abstract

As technology scales, energy consumption is becoming an important issue in high-performance VLSI microprocessor designs. Often the critical path of these microprocessors is in the data-path of arithmetic units, resulting in high energy consumption along the data-path. We are developing an optimization method that can achieve energy saving versus delay-based optimization at equal performance. It reveals that the source of energy saving lays in the balance of delay and energy consumption among different stages of a circuit. The energy saving is significant, 30%ƒ{50%. The results are confirmed with simulation, using Fujitsu¡¦s 0.11ƒÝm, 1.2V CMOS technology.